1. Field of the Invention
The present invention relates to a memory selection circuit for selecting an area to be written/read into or from a memory which is formed of a plurality of divided memory areas.
2. Description of the Related Art
FIG. 5 is a block diagram showing an example of the construction of a microcomputer 1 equipped with a conventional memory selection circuit. The microcomputer 1 has memories M1, M2, M3, and M4 all of which have the same memory capacity. A writing/reading operation of the microcomputer 1 is controlled by its central processing unit (hereinafter abbreviated as CPU). In the following explanation, it is assumed that each memory M1 to M4 has a memory capacity of 2K bytes and has an address range shown in Table 1 below.
TABLE 1 ______________________________________ Address Range ______________________________________ Memory M1 ##STR1## M2 ##STR2## M3 ##STR3## M4 ##STR4## ______________________________________
In this description, in a case where a CPU 2 outputs a 20-bit (A0 to A19) address, an address bus 3, which is directly connected between each of the memories M1, M2, M3, and M4 and the CPU 2, is formed from 11 signal lines for bits A0 to A10. The remaining upper-order bits A11 to A19 are inputted to a memory selection circuit 4, and selection signals CS1, CS2, CS3 and CS4, for respectively selecting memories M1 to M4, are respectively inputted to the memories M1 to M4. That is, regarding an address supplied to each memory M1 to M4, the lower-order bits A0 to A10 are supplied in common to the memories M1 to M4, and one of the selection signals CS1, CS2, CS3 and CS4 is outputted. As a result, one of the corresponding memories M1 to M4 is accessed by the lower-order bits A0 to A10.
Data that is written/read is inputted and outputted between the CPU 2 and the memories M1 to M4 via a data bus 5. The CPU 2 outputs a write control signal W and a read control signal R for switching each of the memories M1 to M4 between a write state and a read state. These control signals W and R can be inputted to the memories M1 to M4 respectively selected by one of the selection signals CS1, CS2, CS3 and CS4.
In the microcomputer 1, the memory selection circuit 4, which outputs one of the selection signals CSi (i=1 to 4), depending on the content of the upper-order bits A11 to A19 of an address signal received from the CPU 2, has a circuit arrangement corresponding to each respective capacity of the memories M1 to M4.
Accordingly, if each respective capacity of the memories M1 to M4 is changed from 2K bytes to, for example, 1K or 4K bytes, the circuit arrangement of the memory selection circuit 4 must be changed so as to correspond to the new memory capacity. That is, in developing the microcomputer 1, the memory selection circuit 4 of the type which corresponds to each kind of expected memory capacity needs to be prepared. Hence, much labor and time are required to develop the microcomputer 1 and problems arise in that the manufacture thereof takes time and the number of parts required increases.